Im working on an FPGA-based NES emulator project: https://github.com/jpdoane/nesfpga. The basics are mostly functional and Im now working on bug fixes and adding more mappers. Ideally I'd love to achieve perfect cycle accuracy, partially as a goal in and of itself, but mainly because it facilitates overall troubleshooting if I can directly compare my logs to a known good trace and chase down any differences as bugs. Ive been using Mesen (v2.0.0) as a reference emulator for this, and am currently trying to get MMC3 working using SMB3. Im having a difficult timing getting my IRQ timings to match, and looking more closely at the timing, Im struggling to figure out what the underlying logic must be.
The following two Mesen traces are from SMB3, during the IRQ on scanlines 192 from frames 12 and 15. In both cases, the actual MMC3 IRQ is generated on dot 261. Notice that on frame 12, the interrupt executes after the LDA instruction, which occurs at dot 257. But on frame 15, the BPL instruction occurs at dot 259, followed by the LDA instruction at dot 268, before the interrupt executes. Both LDA and BPL instructions are 3 cycles long, and presumably interrupt timing would be the same for each. I can't figure out why does the interrupt in frame 15 is delayed - Is there some difference between instruction types or some other hidden state that Im not accounting for?
Secondary question: Does this behavior from Mesen match that of real hardware? If not, is there another emulator that would be better to use as "ground truth" for this level of granularity?
frame 12:frame 15:
The following two Mesen traces are from SMB3, during the IRQ on scanlines 192 from frames 12 and 15. In both cases, the actual MMC3 IRQ is generated on dot 261. Notice that on frame 12, the interrupt executes after the LDA instruction, which occurs at dot 257. But on frame 15, the BPL instruction occurs at dot 259, followed by the LDA instruction at dot 268, before the interrupt executes. Both LDA and BPL instructions are 3 cycles long, and presumably interrupt timing would be the same for each. I can't figure out why does the interrupt in frame 15 is delayed - Is there some difference between instruction types or some other hidden state that Im not accounting for?
Secondary question: Does this behavior from Mesen match that of real hardware? If not, is there another emulator that would be better to use as "ground truth" for this level of granularity?
frame 12:
Code:
A81E BPL $A81C A:00 X:00 Y:00 S:FB P:02 V:192 H:248 Fr:12 Cycle:349493A81C LDA $10 = $00 A:00 X:00 Y:00 S:FB P:02 V:192 H:257 Fr:12 Cycle:349496F795 SEI A:00 X:00 Y:00 S:F8 P:06 V:192 H:287 Fr:12 Cycle:349506Code:
A81E BPL $A81C A:00 X:00 Y:00 S:FB P:02 V:192 H:259 Fr:15 Cycle:438838A81C LDA $10 = $00 A:00 X:00 Y:00 S:FB P:02 V:192 H:268 Fr:15 Cycle:438841F795 SEI A:00 X:00 Y:00 S:F8 P:06 V:192 H:298 Fr:15 Cycle:438851Statistics: Posted by jpdoane — Sat Dec 30, 2023 8:48 am — Replies 2 — Views 194