Hello! I have some NES CPU questions, for the people who've studied it to this degree!
So, I understand that reading from 4015 is internal to the CPU, so this data will never appear on the (external) databus, the CPU data pins and anything connected to them, but I have more related questions:
• Will the CPU address pins change to reflect the address for 4015 when reading/writing to this (or indeed to any address in this 4000-401F range), as they would for any other address?
• If they do, will reading from something on the bus at one of these addresses besides 4015 actually result in a correct read? (4016 & 4017 must, for any bits not open bus) Would reading 4015 also suffer bus conflicts if something else were on the bus there?
• Do the CPU data pins change to reflect writes for any address that it writes to in the 4000-401F range? For example, do 4016 writes appear in full on the data pins as well as the low 3 bits on out 0,1,2? Would other writes appear?
• And finally, when the PPU is writing to its palette, does it set its external address pins and latch them (like, I understand, it does when reading its palette), and then set data pins to reflect the actual palette data it's writing, the same as with an actual write to nametable ram, but, presumably, minus the part where it sets the write pin to write? (Or the read pin to read)
Does anyone know much about this sort of behaviour? Has anyone tested this stuff (guessing you'd need a lot more equipment than I have access to), or studied the online simulation thing in these areas? (I wouldn't have a clue where to look).
Cheers!
So, I understand that reading from 4015 is internal to the CPU, so this data will never appear on the (external) databus, the CPU data pins and anything connected to them, but I have more related questions:
• Will the CPU address pins change to reflect the address for 4015 when reading/writing to this (or indeed to any address in this 4000-401F range), as they would for any other address?
• If they do, will reading from something on the bus at one of these addresses besides 4015 actually result in a correct read? (4016 & 4017 must, for any bits not open bus) Would reading 4015 also suffer bus conflicts if something else were on the bus there?
• Do the CPU data pins change to reflect writes for any address that it writes to in the 4000-401F range? For example, do 4016 writes appear in full on the data pins as well as the low 3 bits on out 0,1,2? Would other writes appear?
• And finally, when the PPU is writing to its palette, does it set its external address pins and latch them (like, I understand, it does when reading its palette), and then set data pins to reflect the actual palette data it's writing, the same as with an actual write to nametable ram, but, presumably, minus the part where it sets the write pin to write? (Or the read pin to read)
Does anyone know much about this sort of behaviour? Has anyone tested this stuff (guessing you'd need a lot more equipment than I have access to), or studied the online simulation thing in these areas? (I wouldn't have a clue where to look).
Cheers!
Statistics: Posted by tommycom — Mon May 27, 2024 5:03 pm — Replies 7 — Views 391