Question about documentation and BUS

Hi folks,

The question is: does /ROMSEL (on the cartridge slot) is LOW (active) even if the CPU is not reading the ROM? ($8000–$FFFF - this is, M2 LOW and A15 HIGH)

Just to explain from where my question come from:

In this doc page https://www.nesdev.org/wiki/Cartridge_connector it states that:

/ROMSEL: This pin outputs the logical NAND of M2 and CPU A15. It is low when the CPU reads or writes to $8000–$FFFF and when the address is stable, allowing to enable ROM chips directly. Advanced mappers use more logic between this pin and the actual PRG /CE (to avoid bus conflicts, for example). Using this signal is the only way to determine the state of A15, so it's needed for any mappers doing any address decoding.

Does it need to be LOW when A15 is HIGH (address $8000–$FFFF) and M2 is LOW?

Also, in the docs, it is stated in the cart schematic that "/ROMSEL (/A15 + /M2)" = NOT(A15) OR NOT (M2) = NAND (A15, M2)

Just to make clear, ROMSEL = NAND(A15,M2) and in the cartidgre slot we have /ROMSEL, that is, NOT (ROMSEL), is that right? I was a little confused in this part.

Thanks in advance guys

Statistics: Posted by odelot — Mon Jun 03, 2024 5:13 am — Replies 6 — Views 321

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