PPU Palette RAM Access Questions

I have a few questions about how the PPU does Palette RAM Addressing, as i feel the Wiki is vague about this.
When the PPU reads from Palette RAM ($3Fxx), does it still pull /RD low? The Pinout page says it doesn't pull /WR low when writing there, but nothing about /RD.
I'd also like to know if it sets the correct Address pins, and what happens when data is present on the Bus during PALRAM reads. I'd assume the Data either is ignored or ORed together.
I'm just kind of curious. I do have an NES, but not the right equipment to figure this out.

Any answers are appreciated

Statistics: Posted by PizzerLover123 — Mon Nov 04, 2024 10:37 am — Replies 3 — Views 124

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