Hello to everyone,
I have been reading about DMC and its DMA on the wiki and trying to implement it with mixed results (and feelings![:lol:]( "Laughing")
).
Putting for now aside the exact way DMA steals CPU cycles, i have some very strange results (the "DMC DMA during OAM DMA" test ROM shows results like 4000 cycles in one case and 114 in other cases, the correct being about 514+, while debugging my emulator clearly shows that the OAM dma takes about 513 cycles at the time the last OAM DMA byte is fetched). Which all seems very odd to me. Ill dig into the rest ROM source to better understand it.
I have some questions about the DMC playback in general.
1. It looks like the sample length, if not set, is always 1. Is this correct.
2. If sample address is not set, is 0xC000 assumed?
3. If TimerPeriod is not set, is 0 assumed (428 CPU ccs)?
4. How does the current sample address wrap around when incremented?
5. We know that there are two 1-byte registers holding sample data during DMC playback - the ReaderBuffer and the ShiftRegister.
Whenever the ShiftRegister shifts out (at the rate of CPUSpeed / TimerPeriod) all of its 8 bits to the DAC counter, the ReaderBuffer is copied into it and if BytesRemaing is more than 0, a new DMA cycle begins, to fetch a new sample into the ReaderBuffer.
If there are no more samples and looping is disabled, IRQ flag is raised if DMC IRQ is enabled.
There are many questions and edge cases with this:
- if looping is disabled, is IRQ raised when the last sample bit is shifted out to the DAC counter (all 8 bits are shifted out and ReaderBuffer is empty)?
- If looping is enabled, when does the first DMA of the second sample repetition begin (will there be a one DMA worth of time "gap" between repetitions)?
- what happens to the ReaderBuffer and ShiftRegister if playback is stopped in the middle of a sample? Can it be resumed or it can only be restarted?
- What means to "restart" the current sample. A new DMA to fetch its first byte will begin as soon as ShiftRegister has BitsRemaining = 0 and ReaderBuffer is empty?
I have been reading about DMC and its DMA on the wiki and trying to implement it with mixed results (and feelings
).Putting for now aside the exact way DMA steals CPU cycles, i have some very strange results (the "DMC DMA during OAM DMA" test ROM shows results like 4000 cycles in one case and 114 in other cases, the correct being about 514+, while debugging my emulator clearly shows that the OAM dma takes about 513 cycles at the time the last OAM DMA byte is fetched). Which all seems very odd to me. Ill dig into the rest ROM source to better understand it.
I have some questions about the DMC playback in general.
1. It looks like the sample length, if not set, is always 1. Is this correct.
2. If sample address is not set, is 0xC000 assumed?
3. If TimerPeriod is not set, is 0 assumed (428 CPU ccs)?
4. How does the current sample address wrap around when incremented?
5. We know that there are two 1-byte registers holding sample data during DMC playback - the ReaderBuffer and the ShiftRegister.
Whenever the ShiftRegister shifts out (at the rate of CPUSpeed / TimerPeriod) all of its 8 bits to the DAC counter, the ReaderBuffer is copied into it and if BytesRemaing is more than 0, a new DMA cycle begins, to fetch a new sample into the ReaderBuffer.
If there are no more samples and looping is disabled, IRQ flag is raised if DMC IRQ is enabled.
There are many questions and edge cases with this:
- if looping is disabled, is IRQ raised when the last sample bit is shifted out to the DAC counter (all 8 bits are shifted out and ReaderBuffer is empty)?
- If looping is enabled, when does the first DMA of the second sample repetition begin (will there be a one DMA worth of time "gap" between repetitions)?
- what happens to the ReaderBuffer and ShiftRegister if playback is stopped in the middle of a sample? Can it be resumed or it can only be restarted?
- What means to "restart" the current sample. A new DMA to fetch its first byte will begin as soon as ShiftRegister has BitsRemaining = 0 and ReaderBuffer is empty?
Statistics: Posted by EvtimDjerekarov — Tue Nov 12, 2024 3:43 am — Replies 1 — Views 156