So a goal I've had for a long time but still haven't achieved is an intimate understanding of precisely what is happening in the circuit on a computer (and using the NES as a particular example) when the CPU is expressing a given address on the address bus. First an explanation of the bits I do think I understand, although happy to be corrected:
An operation is decoded by the CPU and found to involve a memory access. The result is that the pins A15-A0 are each set to logic-low or logic-high depending on that specific bit in the 16 bit address. So for instance an address of 0x2000, this results in pin A13 having a logic-high current while all the other pins at that instant have a logic-low current. If you trace the connections of those pins out on the board, presumably this has some effect of having the PPU accept the state of the other connected address pins as the address for a memory access cycle.
This is where it breaks down for me. I've read a bit about multiplexers and made some bad assumptions that there is some chip between the CPU and all the things in its memory map that "plumbs out" the various address lines to IC #1 if A13 is logic-high, but IC #2 if A13 is logic low, but I've since come to the conclusion I was wrong on that because it doesn't seem like there's some master chip that all of the address lines enter and then that send out several sets of address lines to separate components. So to get to the bottom of it, I opened up my NES and started tracing the address lines with a pin. From what I can tell, lines that affect multiple peripherals appear to have circuit connections to *all* those peripherals, although my circuit reading is only about half baked.
So is it that the low address lines are connected to everything they would influence access on, and then the high lines are connected in certain ways to indicate which chip should expect to find data or otherwise put data on the data bus? So to use an example with this understanding:
I perform an operation that reads from memory address $2002. This sets A13 high, which however it does it on the board, indicates that the memory device that should emit a value on the data bus is the PPU. The A13 is "stripped off" by whatever this is, sending just at least A2-A0 to the PPU (addressing 0x0-0x7 locally to that IC). The PPU sees a logic-high A1 flanked by logic-low A2 and A0, interprets this in the circuitry as "expose the status on the data bus", and puts the relevant data on D7-D0 which the CPU then reads on the next memory read step.
Given my newer assumption that the lower address lines touch *all* the devices they can influence, the high order bits just influence in some way which one of those gets to touch the data bus that cycle, this would mean that *both* the PPU *and* WRAM IC are receiving logic-high on their respective A1 pins, and so internally is putting the byte at 0x2 on the data bus, it just so happens the WRAM data bus, for this cycle, is not the one communicating with CPU D7-D0 because instead it is the PPU data bus connected, again by whatever "switch is flipped" by A13 coming out of the CPU being logic-high.
To summarize, my assumption at present is that logic-high on high pins like A15, A14, A13, influence arbitration of the *data bus* rather than deciding where the lower address lines will actually connect, they simply connect to everything, but the selection of high bits then influences which of the peripheral data buses will actually be connected to the CPU data bus for that given memory cycle.
Any thoughts? Am I way off base? Does this apply to computer situations as well with things like northbridges just being this same arbitration on steroids? Needless to say, at the root of it all is trying to understand how a single set of address pins coming out of a physical CPU IC can result in accesses on the specific destination IC when there are multiple and whether the implementation details result in low address lines being connected to (and technically influencing) multiple ICs at once while data bus arbitration is what is responsible for the data bus of the CPU actually being connected to the lines from the correct IC.
An operation is decoded by the CPU and found to involve a memory access. The result is that the pins A15-A0 are each set to logic-low or logic-high depending on that specific bit in the 16 bit address. So for instance an address of 0x2000, this results in pin A13 having a logic-high current while all the other pins at that instant have a logic-low current. If you trace the connections of those pins out on the board, presumably this has some effect of having the PPU accept the state of the other connected address pins as the address for a memory access cycle.
This is where it breaks down for me. I've read a bit about multiplexers and made some bad assumptions that there is some chip between the CPU and all the things in its memory map that "plumbs out" the various address lines to IC #1 if A13 is logic-high, but IC #2 if A13 is logic low, but I've since come to the conclusion I was wrong on that because it doesn't seem like there's some master chip that all of the address lines enter and then that send out several sets of address lines to separate components. So to get to the bottom of it, I opened up my NES and started tracing the address lines with a pin. From what I can tell, lines that affect multiple peripherals appear to have circuit connections to *all* those peripherals, although my circuit reading is only about half baked.
So is it that the low address lines are connected to everything they would influence access on, and then the high lines are connected in certain ways to indicate which chip should expect to find data or otherwise put data on the data bus? So to use an example with this understanding:
I perform an operation that reads from memory address $2002. This sets A13 high, which however it does it on the board, indicates that the memory device that should emit a value on the data bus is the PPU. The A13 is "stripped off" by whatever this is, sending just at least A2-A0 to the PPU (addressing 0x0-0x7 locally to that IC). The PPU sees a logic-high A1 flanked by logic-low A2 and A0, interprets this in the circuitry as "expose the status on the data bus", and puts the relevant data on D7-D0 which the CPU then reads on the next memory read step.
Given my newer assumption that the lower address lines touch *all* the devices they can influence, the high order bits just influence in some way which one of those gets to touch the data bus that cycle, this would mean that *both* the PPU *and* WRAM IC are receiving logic-high on their respective A1 pins, and so internally is putting the byte at 0x2 on the data bus, it just so happens the WRAM data bus, for this cycle, is not the one communicating with CPU D7-D0 because instead it is the PPU data bus connected, again by whatever "switch is flipped" by A13 coming out of the CPU being logic-high.
To summarize, my assumption at present is that logic-high on high pins like A15, A14, A13, influence arbitration of the *data bus* rather than deciding where the lower address lines will actually connect, they simply connect to everything, but the selection of high bits then influences which of the peripheral data buses will actually be connected to the CPU data bus for that given memory cycle.
Any thoughts? Am I way off base? Does this apply to computer situations as well with things like northbridges just being this same arbitration on steroids? Needless to say, at the root of it all is trying to understand how a single set of address pins coming out of a physical CPU IC can result in accesses on the specific destination IC when there are multiple and whether the implementation details result in low address lines being connected to (and technically influencing) multiple ICs at once while data bus arbitration is what is responsible for the data bus of the CPU actually being connected to the lines from the correct IC.
Statistics: Posted by segaloco — Wed Nov 06, 2024 1:29 pm — Replies 10 — Views 232